Manufacturing fan-out wafer level packaging

ABSTRACT

Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface and a bond pad defined on the top surface, and a substrate having a cavity. An adhesive layer is positioned between a top surface of the cavity and the bottom surface of the integrated circuit, and a bump is positioned proximate a top surface of the fan-out wafer level packaging, the bump spaced apart from the integrated circuit. A redistribution layer is configured to electrically couple the bond pad of the integrated circuit to the bump.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.12/330,044, filed Dec. 8, 2008, now pending, which application isincorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

This description generally relates to the field of chip packaging, andmore particularly to fan-out wafer level packaging.

2. Description of the Related Art

Redistributing the bond pads of integrated circuits (“ICs”) in chippackages is becoming increasingly common. In general, the redistributionprocess converts peripheral wire bond pads on an IC to an area array ofsolder bumps via a redistribution layer. The resulting fan-out waferlevel packaging may have a larger solder bump bonding area and may bemore easily integrated into electronic devices and larger chip packages.

Conventionally, a backside of an IC is first encapsulated in a moldingcompound. A plurality of dielectric layers and redistribution layers arethen deposited on a front side of the IC to form electrical connectionsbetween wire bond pads on the IC and redistributed solder bump bondpads. Finally, solder bumps are formed at the redistributed bond padlocations, and the fan-out wafer level packaging is ready to be solderedto a printed circuit board.

There remains a need in the art, however, for an improved method ofmanufacturing fan-out wafer level packaging.

BRIEF SUMMARY

In one embodiment, a method of manufacturing fan-out wafer levelpackaging may be summarized as comprising: forming a cavity in asubstrate; forming an adhesive layer on at least a portion of a topsurface of the cavity; placing an integrated circuit having a topsurface and a bond pad on the top surface within the cavity, at least aportion of a bottom surface of the integrated circuit contacting theadhesive layer; forming a redistribution layer configured toelectrically couple the bond pad of the integrated circuit to aredistributed bond pad; and forming a bump at the redistributed bondpad.

In another embodiment, fan-out wafer level packaging may be summarizedas comprising: an integrated circuit having a top surface, a bottomsurface and a bond pad defined on the top surface; a substrate having acavity; an adhesive layer positioned between a top surface of the cavityand the bottom surface of the integrated circuit; a bump positionedproximate a top surface of the fan-out wafer level packaging, the bumpspaced apart from the integrated circuit; and a redistribution layerconfigured to electrically couple the bond pad of the integrated circuitto the bump.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

In the drawings, identical reference numbers identify similar elementsor acts. The sizes and relative positions of elements in the drawingsare not necessarily drawn to scale. For example, the shapes of variouselements and angles are not drawn to scale, and some of these elementsare enlarged and positioned to improve drawing legibility. Further, theparticular shapes of the elements as drawn, are not intended to conveyany information regarding the actual shape of the particular elements,and have been solely selected for ease of recognition in the drawings.

FIG. 1 is a cross-sectional, side, schematic view of fan-out wafer levelpackaging, according to one embodiment.

FIG. 2 is a flow chart illustrating one method of manufacturing thefan-out wafer level packaging of FIG. 1, according to one embodiment.

FIG. 3 is a top view of a substrate wafer including a plurality ofcavities, including an enlarged top view of one of the cavities,according to one embodiment.

FIG. 4A is a cross-sectional, side view of one of the plurality ofcavities of FIG. 3, according to one embodiment.

FIG. 4B is a cross-sectional, side view of a cavity formed from stackedlayers of substrate material, according to one embodiment.

FIG. 5 is a top view of a wafer including a plurality of integratedcircuits, according to one embodiment.

FIG. 6 is a cross-sectional, side view of the wafer of FIG. 5, withadhesive tape affixed to a bottom of the wafer, according to oneembodiment.

FIG. 7 is a cross-sectional, side view of one of the integrated circuitsof the wafer of FIG. 6 after a dicing process, according to oneembodiment.

FIG. 8 is a cross-sectional, side view of the integrated circuit of FIG.7 placed within the cavity of FIG. 4A, according to one embodiment.

FIG. 9A is a cross-sectional, side view of the cavity of FIG. 4Apartially filled with an adhesive glue, according to one embodiment.

FIG. 9B is a cross-sectional, side view of an integrated circuit placedwithin the cavity partially filled with the adhesive glue of FIG. 9A,according to one embodiment.

FIG. 10 is a cross-sectional, side view of a first dielectric layerformed over at least a portion of the integrated circuit and cavity ofFIG. 8, according to one embodiment.

FIG. 11 is a cross-sectional, side view of a redistribution layer formedover at least a portion of the first dielectric layer of FIG. 10,according to one embodiment.

FIG. 12 is a cross-sectional, side view of a second dielectric layerformed over at least a portion of the redistribution layer of FIG. 11,according to one embodiment.

FIG. 13 is a cross-sectional, side view of a redistributed bond padformed over at least a portion of the redistribution layer of FIG. 11,according to one embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the following description, certain specific details are set forth inorder to provide a thorough understanding of various disclosedembodiments. However, one skilled in the relevant art will recognizethat embodiments may be practiced without one or more of these specificdetails, or with other methods, components, materials, etc. In otherinstances, well-known structures and methods associated with integratedcircuits and semiconductor manufacturing/packaging processes have notbeen shown or described in detail to avoid unnecessarily obscuringdescriptions of the embodiments.

Unless the context requires otherwise, throughout the specification andclaims which follow, the word “comprise” and variations thereof, suchas, “comprises” and “comprising” are to be construed in an open,inclusive sense, that is, as “including, but not limited to.”

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure or characteristicdescribed in connection with the embodiment is included in at least oneembodiment. Thus, the appearances of the phrases “in one embodiment” or“in an embodiment” in various places throughout this specification arenot necessarily all referring to the same embodiment. Furthermore, theparticular features, structures, or characteristics may be combined inany suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singularforms “a,” “an,” and “the” include plural referents unless the contextclearly dictates otherwise. It should also be noted that the term “or”is generally employed in its sense including “and/or” unless the contextclearly dictates otherwise.

The headings and Abstract of the Disclosure provided herein are forconvenience only and do not interpret the scope or meaning of theembodiments.

Description of an Exemplary Fan-out Wafer Level Packaging

FIG. 1 shows fan-out wafer level packaging 100, according to oneillustrated embodiment. The fan-out wafer level packaging 100 may beconfigured to protect an integrated circuit 102 from the externalenvironment. In one embodiment, the fan-out wafer level packaging 100includes a plurality of bumps 104 electrically coupled to the integratedcircuit 102, and the fan-out wafer level packaging 100 may thus enableelectrical connections to be formed between the integrated circuit 102and external circuitry. In other embodiments, other electricallyconductive structures may be formed along an external surface of thefan-out wafer level packaging 100 in order to enable such electricalconnections with the integrated circuit 102.

The integrated circuit 102 may include any of a variety of electroniccircuitry. For example, the integrated circuit 102 may comprise acontroller for an electronic computing device, or a computer-readablememory. In different embodiments, the integrated circuit 102 may beformed using any of a variety of semiconductor fabrication processes. Inone embodiment, the integrated circuit 102 is defined by layers ofsemi-conducting, dielectric and conducting materials deposited onto asemiconductor substrate in accordance with pre-defined patterns.

As illustrated, the integrated circuit 102 may include a top surface 106and a bottom surface 108. Of course, the terms, top and bottom, referonly to the orientation of the respective surfaces in FIG. 1, and shouldnot be understood to imply any absolute positioning of the integratedcircuit 102. Although not visible in FIG. 1, the integrated circuit 102may further include one or more bond pads defined on the top surface106. The number of bond pads may vary greatly depending upon theparticular application for the integrated circuit 102. For example,controller circuitry may require more bond pads defining input/outputsthan memory circuitry. The bond pads may comprise any type of conductingmaterial, such as copper, silver or gold.

The integrated circuit 102 may have any of a variety of shapes andsizes. In one embodiment, the integrated circuit 102 has a generallyrectilinear top surface 106. For example, the top surface 106 may have agenerally square shape. In other embodiments, more irregular shapes maydefine the integrated circuit 102.

The fan-out wafer level packaging 100 may further comprise a substrate110 having a cavity 112 defined therein. The substrate 110 may compriseany of a variety of dielectric materials. In one embodiment, thesubstrate 110 comprises FR-4 material (similar to that used to fabricateprinted circuit boards). The material comprising the substrate 110 mayalso be chosen to provide substantial rigidity to the fan-out waferlevel packaging 100.

The substrate 110, like the integrated circuit 102, may have any of avariety of shapes and sizes. As illustrated, the substrate 110 is largerthan the integrated circuit 102, such that the integrated circuit 102may fit at least partially within the cavity 112 defined within thesubstrate 110. The substrate 110 may further have a generallyrectilinear shape, such that the shape of the substrate 110 and theshape of the integrated circuit 102 are geometrically similar.

In one embodiment, the cavity 112 defined within the substrate 110 issubstantially larger than the integrated circuit 102, such that theintegrated circuit 102 may be positioned entirely within the cavity 112(as illustrated in FIG. 1). The cavity 112 may also have a generallyrectilinear shape that is geometrically similar to the shape of the topsurface 106 of the integrated circuit 102. In other embodiments, thecavity 112 may define a more complex shape that generally follows thecontours of the integrated circuit 102. In still other embodiments, theshapes of the cavity 112, the substrate 110 and the integrated circuit102 may be independent and dissimilar.

As illustrated in FIG. 1, the fan-out wafer level packaging 100 mayfurther include an adhesive layer 114 positioned between a top surface116 of the cavity 112 and the bottom surface 108 of the integratedcircuit 102. The adhesive layer 114 may comprise any of a variety ofadhesive materials configured to adhere to both the integrated circuit102 and the substrate 110. In some embodiments, the adhesive layer 114comprises an adhesive glue, such as an epoxy. In other embodiments,other materials, such as polyimide, polybenzoxazole or solder resist,may serve as the adhesive layer 114. In still other embodiments, theadhesive layer 114 comprises double-sided tape positioned between thesubstrate 110 and the integrated circuit 102. For example, thedouble-sided tape may include a first adhesive material positionedadjacent the integrated circuit 102, and a second adhesive materialpositioned adjacent the substrate 110. In such an embodiment, the twodifferent adhesive materials may be optimized to adhere to theirrespective surfaces. In still another embodiment, the fan-out waferlevel packaging 100 may not include an adhesive layer 114, and otherstructures may be used to fix the integrated circuit 102 at leastpartially within the cavity 112.

The fan-out wafer level packaging 100 may further include one or morebumps 104 positioned proximate a top surface 118 of the fan-out waferlevel packaging 100. Each of these bumps 104 is spaced apart from theintegrated circuit 102, but may be electrically coupled thereto. Thebumps 104 may comprise any of a variety of solder bumps formed fromdifferent materials. In one embodiment, the bumps 104 comprise lead-freesolder bumps, while, in other embodiments, the bumps 104 include lead aswell as other conductive materials, such as tin. Although three bumps104 are visible in the cross-section of FIG. 1, more or fewer bumps 104may be incorporated into the fan-out wafer level packaging 100 indifferent embodiments. For example, in some embodiments, at least onebump 104 may correspond to each bond pad defined on the top surface 106of the integrated circuit 102.

The bumps 104 may also have any of a variety of sizes. In oneembodiment, the bumps 104 have diameters of between 10 and 200 μm,depending upon their composition, as well as the processes used to formthem.

The fan-out wafer level packaging 100 may further include aredistribution layer 120 configured to electrically couple at least onebond pad of the integrated circuit 102 to a corresponding bump 104. Theredistribution layer 120 may comprise any of a variety of electricallyconductive materials defining at least part of an electrical pathbetween particular bond pads of the integrated circuit 102 andcorresponding bumps 104. For example, the redistribution layer 120 maycomprise copper or gold in some embodiments.

In one embodiment, as illustrated in FIG. 1, the redistribution layer120 itself may define redistributed bond pads (located directlyunderneath corresponding bumps 104), and the bumps 104 may be in directcontact with the redistribution layer 120. However, in otherembodiments, redistributed bond pads may be formed atop theredistribution layer 120 (as illustrated in FIG. 13 and discussed ingreater detail below), and the bumps 104 may be coupled thereto.

The redistribution layer 120 may have any of a variety of thicknesses.In one embodiment, the redistribution layer 120 may be between 1 and 10μm thick. Such a substantial thickness may facilitate the use of theredistribution layer 120 itself as a redistributed bond pad withlead-free bumps. In other embodiments, the redistribution layer 120 maybe at least 1 μm thick. In such embodiments, it may be desirable to usethe redistribution layer 120 with a separate redistributed bond pad toform the final interface with a corresponding bump 104.

The fan-out wafer level packaging 100 may further include dielectriclayers 122, 124. Such dielectric layers 122, 124 may add structuralintegrity to the fan-out wafer level packaging 100, while keepingconductive elements of the fan-out wafer level packaging 100electrically insulated from one another. In one embodiment, a firstdielectric layer 122 extends at least partially over the top surface 106of the integrated circuit 102. The first dielectric layer 122 may defineat least one bond pad via, through which the redistribution layer 120may contact a corresponding bond pad of the integrated circuit 102. Twosuch bond pad vias are illustrated in the cross-sectional view ofFIG. 1. Of course, in other embodiments, more or fewer bond pad vias maybe defined. As illustrated in FIG. 1, at least a portion of the firstdielectric layer 122 may also be positioned between a sidewall of thecavity 112 and an opposing sidewall of the integrated circuit 102. Infact, the sidewalls of the integrated circuit 102 may be substantiallysurrounded by the first dielectric layer 122 in some embodiments. Thefirst dielectric layer 122 may also extend over substantially all of atop surface 126 of the substrate 110, as illustrated in FIG. 1.

In one embodiment, a second dielectric layer 124 extends at leastpartially over the redistribution layer 120. The second dielectric layer124 may define at least one redistribution via therethrough that extendsto the redistribution layer 120. Three such redistribution vias areillustrated in the cross-sectional view of FIG. 1. Of course, in otherembodiments, more or fewer redistribution vias may be defined. In oneembodiment, each redistribution via through the second dielectric layer124 may correspond to exactly one bond pad via through the firstdielectric layer 122.

In one embodiment, the first dielectric layer 122 and the seconddielectric layer 124 comprise the same dielectric material. For example,a photosensitive polymer, such as polyimide, polybenzoxazole or solderresist, may be used to define both the first dielectric layer 122 andthe second dielectric layer 124. In other embodiments, differentmaterials may be used to define the two dielectric layers 122, 124.

The first dielectric layer 122 may have any of a variety of thicknesses.In one embodiment, the first dielectric layer 122 may be betweenapproximately 5 and 10 μm thick, as measured from the top surface 126 ofthe substrate 110 to the redistribution layer 120. The second dielectriclayer 122 may also be formed to define any of a variety of thicknesses.In one embodiment, a thickness of the second dielectric layer 124 may begreater than 2 μm added to a thickness of the redistribution layer 120.

Description of an Exemplary Method for Manufacturing Fan-out Wafer LevelPackaging

FIG. 2 illustrates a flow diagram for a method 200 of manufacturingfan-out wafer level packaging, according to one embodiment. This method200 will be discussed in the context of the fan-out wafer levelpackaging 100 of FIG. 1 with reference to FIGS. 3-13, which illustrateassociated structures as well as the fan-out wafer level packaging 100at varying stages during the manufacturing process. However, it may beunderstood that the acts disclosed herein may also be executed tomanufacture a variety of differently configured fan-out wafer levelpackaging, in accordance with the described method.

As described herein, all of the acts comprising the method 200 may beorchestrated by a manufacturing processor or controller based at leastin part on execution of computer-readable instructions stored in memory.In other embodiments, a hardware implementation of all or some of theacts of method 200 may be used.

The method begins at 202, when a cavity 112 is formed in a substrate110. The substrate 110 may comprise any of a variety of substrates. Inone embodiment, as illustrated in FIG. 3, a unitary wafer 300 ofsubstrate material is provided. The wafer 300 may comprise any of avariety of dielectric materials. As illustrated, the wafer 300 may beprocessed to form a plurality of cavities 112. In one embodiment, theplurality of cavities 112 are milled simultaneously in the unitary pieceof substrate material. In another embodiment, each cavity 112 may bemilled or otherwise formed in a separate process. In still anotherembodiment, a chemical etching process may be used to form the cavities112 in the wafer 300.

After the cavities 112 have been formed, the wafer 300 may be divided(e.g., laser-cut or die sawed) to form a plurality of substrates 110.Each of these substrates 110 may then be used in the manufacture ofcorresponding fan-out wafer level packaging 100 in accordance with theacts described below. In another embodiment, the wafer 300 may beprocessed as a whole to form a plurality of unseparated fan-out waferlevel packaging, before a dividing process is executed to define thefinal substrates 110 and separate fan-out wafer level packaging 100.

As illustrated in FIG. 3, each of the cavities 112 may definesubstantially rectilinear openings. In some embodiments, the shapes ofthe cavities 112 are chosen to generally correspond to a shape ofcorresponding integrated circuits 102. In other embodiments, thecavities 112 may define more complex shapes. With reference to FIG. 4A,a cross-sectional, side view of a substrate 110 and corresponding cavity112 is illustrated.

In other embodiments, the cavity 112 may be formed in the substrate 110by other manufacturing processes. For example, as illustrated in FIG.4B, multiple layers 410 a, 410 b of substrate material may be stacked todefine the cavity 112. In one embodiment, a first layer of substratematerial 410 a is defined by a relatively thin wafer. A second layer ofsubstrate material 410 b may be patterned and cut (or otherwise shaped)in order to define an opening of the cavity 112. These two layers 410 a,410 b may then be coupled together via at least one adhesive layer 412interposed therebetween. Thus, the substrate 110 may comprise one ormore components coupled together to form the cavity 112.

Integrated circuits 102 may also be formed by any of a variety ofmanufacturing processes. In one embodiment, as illustrated in FIG. 5, awafer 500 including a plurality of integrated circuits 102 is provided.The wafer 500 may be processed in accordance with a variety ofsemiconductor processing techniques to form the integrated circuits 102,and, in one embodiment, each of the integrated circuits 102 definedwithin the wafer 500 may be similarly configured. The wafer 500 may thenbe divided (e.g. by laser-cutting or die sawing) to define theindividual integrated circuits 102. Although illustrated as round, thewafer 500 may also comprise a square panel ranging in size from 8″×8″ upto 12″×12″.

At act 204, an adhesive layer 114 is formed on at least a portion of atop surface 116 of the cavity 112. As described above, the adhesivelayer 114 may comprise any of a variety of adhesive materials, such asdouble-sided tape or adhesive glue.

In one embodiment, as illustrated in the cross-sectional, side view ofFIG. 6, double-sided tape 502 may first be affixed to a bottom surface504 of the wafer 500. In such an embodiment, the double-sided tape 502may thus be affixed to respective bottom surfaces 108 of each integratedcircuit 102 before the integrated circuits 102 are placed within theirrespective cavities 112. The wafer 500 and the double-sided tape 502 maythen be cut in a single process in order to define the integratedcircuits 102 and corresponding pieces of double-sided tape 502, asillustrated in FIG. 7.

When double-sided tape 502 has been thus adhered to the bottom of eachintegrated circuit 102, forming the adhesive layer 114 may includeplacing the double-sided tape 502 into the cavity 112 with theintegrated circuit 102, as illustrated in FIG. 8. The double-sided tape502 may then form the adhesive layer 114 interposed between theintegrated circuit 102 and the top surface 116 of the cavity 112.

In another embodiment, as illustrated in FIG. 9A, the adhesive layer 114may be formed within the cavity 112 by depositing adhesive glue on thetop surface 116 of the cavity 112. This adhesive glue may be depositedwithin the cavity 112 in a variety of ways, including by injection,sputtering, etc.

As may be seen most clearly in FIG. 8, the cavity 112 may have a widthWC that is substantially larger than a width WIC of the integratedcircuit 102, resulting in gaps G to either side of the sidewalls of theintegrated circuit 102. In one embodiment, a ratio of a thickness T ofthe substrate 110 to a difference between the width WC of the cavity 112and the width WIC of the integrated circuit 102 may be greater than orequal to ¼. Such a ratio may facilitate later acts associated withfilling the gaps G with the first dielectric layer 122, as illustratedin FIG. 10. In other embodiments, other ratios for the thickness T ofthe substrate 110 to a difference between the width WC of the cavity 112and the width WIC of the integrated circuit 102 may be employed.

At act 206, an integrated circuit 102 having a top surface 106 and abond pad on the top surface 106 is placed within the cavity 112, atleast a portion of a bottom surface 108 of the integrated circuit 102contacting the adhesive layer 114. In one embodiment, as illustrated inFIG. 8, the double-sided tape 502 may first be affixed to the bottomsurface 108 of the integrated circuit 102, and then the integratedcircuit 102 and the double-sided tape 502 may be placed within thecavity 112 together.

In another embodiment, as illustrated in FIGS. 9A and 9B, an adhesiveglue may first be deposited within the substrate 110 to form theadhesive layer 114, and then the integrated circuit 102 may be placedwithin the cavity 112, such that a bottom surface 108 of the integratedcircuit 102 contacts the adhesive layer 114. As illustrated, as theintegrated circuit 102 is placed within the cavity 112, some of theadhesive glue may be pushed up between the sidewalls of the integratedcircuit 102 and the cavity 112.

The integrated circuit 102 may be placed within the cavity 112 in avariety of ways. For example, in one embodiment, a robotic end effectormay be used to properly position the integrated circuit 102 relative toan opening of the cavity 112, before the integrated circuit 102 isplaced therein. In another embodiment, a human operator may place theintegrated circuit 102 within the cavity 112 manually or by auser-controlled machine. As illustrated, placing the integrated circuit102 within the cavity 112 may include passing the integrated circuit 102through an opening in the substrate 110 into the cavity 112. Thealignment of the integrated circuit 102 within the cavity 112 may berelatively tightly controlled in some manufacturing processes, andvision systems or other mechanisms for controlling this alignment may beused. In one embodiment, the integrated circuit 102 is positioned so asto be substantially centered within the cavity 112.

In one embodiment, the top surface 106 of the integrated circuit 102 andthe top surface 126 of the substrate 110 are substantially aligned asillustrated in the Figures. However, in other embodiments, theintegrated circuit 102 may extend beyond the opening in the substrate110, or the top surface 106 of the integrated circuit 102 may bepositioned well within the cavity 112.

Once the integrated circuit 102 has been placed within the cavity 112,additional chemical, physical or thermal processing may be carried outto cure or harden the adhesive layer 114. For example, the partiallyformed fan-out wafer level packaging 100 of FIG. 9B may be baked toharden the adhesive layer 114.

In one embodiment, as illustrated in FIG. 10, a first dielectric layer122 may be formed extending at least partially over the top surface 106of the integrated circuit 102. The first dielectric layer 122 may beformed to include at least one bond pad via 128 through which at least aportion of a bond pad of the integrated circuit 102 is exposed. Thesebond pad vias 128 may enable subsequent electrical connections to beformed between the bond pads of the integrated circuit 102 and one ormore redistributed bond pads.

As described above, the first dielectric layer 122 may comprise any of avariety of dielectric materials. In one embodiment, the first dielectriclayer 122 comprises a photosensitive polymer, such as polyimide,polybenzoxazole or solder resist.

The first dielectric layer 122 may also be deposited and then patternedto form the bond pad vias 128 by any of a variety of processes. If thefirst dielectric layer 122 comprises a photosensitive polymer, thephotosensitive polymer may first be coated over the substrate 110 andintegrated circuit 102. As illustrated in FIG. 10, the first dielectriclayer 122 may thus cover substantially all of the top surface 126 of thesubstrate 110, and fill the side gaps G between the sidewalls of thecavity 112 and opposing sidewalls of the integrated circuit 102. Afterthis coating, in some embodiments, the first dielectric layer 122 isplanarized. Portions of the first dielectric layer 122 may then beexposed to light (e.g., to ultraviolet light) to create a desiredpatterning in this layer 122. After the light exposure, the exposedportions of the first dielectric layer 122 may then be removed byapplication of a developer solvent if a positive photosensitive polymeris used, or the unexposed portions may be removed if a negativephotosensitive polymer is used. Of course, in other embodiments, otherpatterning processes may be used. For example, a separate photoresistlayer may be deposited on top of the first dielectric layer 122 in orderto define and then transfer a desired pattern to the first dielectriclayer 122.

Additional chemical, physical or thermal processing may be carried outto cure or harden the first dielectric layer 122. For example, thepartially formed fan-out wafer level packaging 100 of FIG. 10 may bebaked to cure the first dielectric layer 122.

At act 208, a redistribution layer 120 configured to electrically couplethe bond pad of the integrated circuit 102 to a redistributed bond padis formed. The redistribution layer 120 may comprise any of a variety ofelectrically conductive materials, as discussed above. As illustrated inFIG. 11, the redistribution layer 120 may be formed over at least aportion of the first dielectric layer 122 and may fill at leastpartially the bond pad via 128. Thus, the redistribution layer 120 maycreate electrical connections between the bond pads of the integratedcircuit 102 and one or more redistributed bond pads through the bond padvias 128.

In one embodiment, after the first dielectric layer 122 has been formed,a seed layer (not shown) may first be sputtered over the firstdielectric layer 122. The seed layer may comprise a metallic thin film,such as copper. This seed layer may thus extend over the entire exposedsurface of the partially formed fan-out wafer level packaging 100 ofFIG. 10. A patterned layer may then be formed over the seed layer usingphotolithography. Any of a variety of photolithographic techniques maybe used to form such a patterned layer over the seed layer. Thepatterned layer may comprise, for example, photoresist material. Thepatterned layer may leave portions of the seed layer exposed in apattern that will eventually define the pattern of the redistributionlayer 120. At least a portion of the seed layer exposed through thepatterned layer may then be plated to form the redistribution layer 120.For example, electrochemical plating or electroless plating may beperformed to create a copper redistribution layer 120. The patternedlayer may then be removed, and the remaining portions of the seed layerthat were not plated may also be removed. Any of a variety of chemicalor physical processes, such as wet etching, may be used to remove theselayers, leaving the patterned redistribution layer 120. Of course, inother embodiments, other techniques for forming a patternedredistribution layer 120 may be used.

As illustrated in FIG. 12, once the redistribution layer 120 has beenformed, a second dielectric layer 124 may be formed extending at leastpartially over the redistribution layer 120 and including at least oneredistribution via 130 through which at least a portion of theredistribution layer 120 is exposed. These redistribution vias 130 maydefine the locations for one or more redistributed bond pads. Asdescribed above, in one embodiment, the redistribution layer 120 mayitself define the redistributed bond pads. In other embodiments, aredistributed bond pad may be formed at least partially within acorresponding redistribution via 130, as described in greater detailbelow with respect to FIG. 13.

As described above, the second dielectric layer 124 may comprise any ofa variety of dielectric materials. In one embodiment, the seconddielectric layer 124 and the first dielectric layer 122 comprise thesame material. For example, the second dielectric layer 124 may comprisea photosensitive polymer, such as polyimide, polybenzoxazole or solderresist.

The second dielectric layer 124 may be deposited and then patterned toform the redistribution vias 130 in a variety of ways. If the seconddielectric layer 124 comprises a photosensitive polymer, thephotosensitive polymer may first be coated over the redistribution layer120 and exposed portions of the first dielectric layer 122. After thiscoating, in some embodiments, the second dielectric layer 124 isplanarized. Portions of the second dielectric layer 124 may then beexposed to light (e.g., to ultraviolet light) to create the desiredpatterning in this layer 124. After the light exposure, the exposedportions of the second dielectric layer 124 may then be removed byapplication of a developer solvent if a positive photosensitive polymeris used, or the unexposed portions may be removed if a negativephotosensitive polymer is used. Of course, in other embodiments, otherpatterning processes may be used. For example, a separate photoresistlayer may be deposited on top of the second dielectric layer 124 inorder to define and then transfer a desired pattern to the seconddielectric layer 124.

Additional chemical, physical or thermal processing may be carried outto cure or harden the second dielectric layer 124. For example, thepartially formed fan-out wafer level packaging 100 of FIG. 12 may bebaked to cure the second dielectric layer 124.

At act 210, a bump 104 is formed at the redistributed bond pad. The bump104 may comprise any of a variety of conductive materials, as describedabove. In one embodiment, the bump 104 may comprise a lead-free bump,although in other embodiments leaded bumps may be used.

In one embodiment, the redistributed bond pad may simply be defined bythe portions of the redistribution layer 120 exposed through theredistribution vias 130, as illustrated in FIG. 12. In such anembodiment, the bumps 104 may be formed by conventional ball bondingtechniques in direct contact with the redistribution layer 120. Thus,the bumps 104 may be formed on the partially formed fan-out wafer levelpackaging 100 of FIG. 12 to form the completed fan-out wafer levelpackaging 100 of FIG. 1.

In other embodiments, after forming the second dielectric layer 124, aredistributed bond pad 132 may be formed at least partially within theredistribution via 130, as illustrated in FIG. 13. Such a redistributedbond pad 132 may comprise an under-bump-metallurgy layer configured tofacilitate the electrical connection formed between the bump 104 and theredistribution layer 120. This redistributed bond pad 132 may be formedby a variety of processes. In one embodiment, the redistributed bond pad132 may be formed by sputtering a compound of either: (a) titanium,nickel and copper, or (b) aluminum, nickel and copper. The sputteredcompound may then be plated with a compound of either: (a) titanium andcopper, (b) titanium, tungsten and copper, or (c) chromium and copper.In another embodiment, the redistributed bond pad 132 may be formed byplating the exposed redistribution layer 120 with at least one of: (a)copper, (b) nickel, or (c) copper and nickel.

The completed fan-out wafer level packaging 100 is illustrated inFIG. 1. In one embodiment, the fan-out wafer level packaging 100 may becoupled to one or more additional chip packages or electronic devicesvia the bumps 104. In other embodiments, one or more additional vias maybe formed through the substrate 110 in order to form additionalelectrical connections on a bottom surface 134 of the substrate 110.That is, these vias may extend through the substrate 110 and the firstdielectric layer 122 in some embodiments in order to connect anelectrical line passing through the substrate 110 with theredistribution layer 120. Bond pads on the top surface 106 of theintegrated circuit 102 may thus be electrically coupled to one or moreadditional bond pads proximate the bottom surface 134 of the substrate110.

The foregoing detailed description has set forth various embodiments ofthe devices and/or processes via the use of block diagrams, schematics,and examples. Insofar as such block diagrams, schematics, and examplescontain one or more functions and/or operations, it will be understoodby those skilled in the art that each function and/or operation withinsuch block diagrams, flowcharts, or examples can be implemented,individually and/or collectively, by a wide range of hardware, software,firmware, or virtually any combination thereof. In one embodiment, thepresent subject matter may be implemented via Application SpecificIntegrated Circuits (ASICs). However, those skilled in the art willrecognize that the embodiments disclosed herein, in whole or in part,can be equivalently implemented in standard integrated circuits, as oneor more programs executed by one or more processors, as one or moreprograms executed by one or more controllers (e.g., microcontrollers),as firmware, or as virtually any combination thereof, and that designingthe circuitry and/or writing the code for the software and or firmwarewould be well within the skill of one of ordinary skill in the art inlight of this disclosure.

When logic is implemented as software and stored in memory, one skilledin the art will appreciate that logic or information can be stored onany computer readable storage medium for use by or in connection withany processor-related system or method. In the context of this document,a memory is a computer readable storage medium that is an electronic,magnetic, optical, or other physical device or means that contains orstores a computer and/or processor program and/or data or information.Logic and/or the information can be embodied in any computer readablestorage medium for use by or in connection with an instruction executionsystem, apparatus, or device, such as a computer-based system,processor-containing system, or other system that can fetch theinstructions from the instruction execution system, apparatus, or deviceand execute the instructions associated with logic and/or information.

The various embodiments described above can be combined to providefurther embodiments. From the foregoing it will be appreciated that,although specific embodiments have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the teachings. Accordingly, the claims are notlimited by the disclosed embodiments.

We/I claim:
 1. A Fan-out wafer level package, comprising: an integratedcircuit having a top surface, a bottom surface and a bond pad defined onthe top surface; a substrate having a cavity; an adhesive layerpositioned between a top surface of the cavity and the bottom surface ofthe integrated circuit; a bump positioned proximate a top surface of thesubstrate, spaced apart from the integrated circuit; and aredistribution layer configured to electrically couple the bond pad ofthe integrated circuit to the bump.
 2. The fan-out wafer level packagingof claim 1, wherein the adhesive layer comprises an adhesive glue. 3.The fan-out wafer level packaging of claim 1, wherein the adhesive layercomprises double-sided tape.
 4. The fan-out wafer level packaging ofclaim 1, further comprising a first dielectric layer extending at leastpartially over the top surface of the integrated circuit, the firstdielectric layer defining a bond pad via, wherein at least a portion ofthe redistribution layer contacts the bond pad of the integrated circuitthrough the bond pad via.
 5. The fan-out wafer level packaging of claim4, further comprising a second dielectric layer extending at leastpartially over the redistribution layer, the second dielectric layerdefining a redistribution via to the redistribution layer.
 6. Thefan-out wafer level packaging of claim 5, further comprising aredistributed bond pad positioned at least partially within theredistribution via.
 7. The fan-out wafer level packaging of claim 1,wherein the redistribution layer defines a redistributed bond pad, andthe bump is in direct contact with the redistribution layer.
 8. Thefan-out wafer level packaging of claim 1, wherein a ratio of a thicknessof the substrate to a difference between a width of the cavity and awidth of the integrated circuit is greater than or equal to ¼.